IEICE Transactions on Communications
Online ISSN : 1745-1345
Print ISSN : 0916-8516
Regular Section
A Novel 400-Gb/s (100-Gb/s × 4) Physical-Layer Architecture Using Low-Power Technology
Masashi KONOAkihiro KANBEHidehiro TOYODAShinji NISHIMURA
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2012 Volume E95.B Issue 11 Pages 3437-3444

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Abstract

A novel 400-Gb/s (100-Gb/s × 4) physical-layer architecture for the next-generation Ethernet — using 100-Gb/s serial (optical single-wavelength) transmission — is proposed. As for the next-generation 400-Gb/s Ethernet, additional requirements from the market, such as power reduction and further miniaturization in addition to attaining even higher transmission speed, must be satisfied. To satisfy these requirements, a 100-Gb/s×4 Ethernet physical-layer architecture is proposed. This architecture uses a 100-Gb/s serial (optical single-wavelength) transmission Ethernet and low-power technologies for a multi-lane transmission Ethernet. These technologies are implemented on a 100-Gb/s serial (optical single wavelength) transmission Ethernet using field-programmable gate arrays (FPGAs). Experimental evaluation of this implementation demonstrates the feasibility of low-power 400-Gb/s Ethernet.

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© 2012 The Institute of Electronics, Information and Communication Engineers
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