Indian Journal of Science and Technology
DOI: 10.17485/ijst/2016/v9i39/101888
Year: 2016, Volume: 9, Issue: 39, Pages: 1-6
Original Article
Altaf O. Mulani1 and P. B. Mane2
1 Electronics and Telecommunication Department, Sinhgad Research Center, S. No. 44/1, Off. Sinhgad Road, Vadgaon Budruk, Pune - 411041, Maharashtra, India; [email protected]
2 AISSMS’s Institute of Information Technology, Pune, Kennedy Road, Near R.T.O., Pune - 411001, Maharashtra, India; [email protected]
Objectives: Present work deals with FPGA based implementation of either watermarking or cryptography alone. Objective is to improve the security using less number of slices with optimum speed. Methods/Statistical Analysis: Digital data is easy to process but it allows illegal users to access the data. For protecting data from illegal use, Digital Rights Management can be used. In this paper, hardware implementation of combined watermarking and cryptography algorithm based watermarking is discussed. With this approach, improved security can be achieved due to use of encryption algorithm. Complete system is designed using Verilog and simulated using Questasim and MATLAB Simulink model. Findings: The highest performance of FPGA based watermarking algorithm alone achieved is 4708 slices at 344.34 MHz. Our combined watermarking and cryptography algorithm utilizes only 2117 at maximum operating frequency of 228.064 MHz. Due to this improved speed and optimized area, our design is economical for real time image processing applications. At the same time, due to use of AES algorithm it is proved that improved security can be achieved.
Keywords: AES, DWT, Encryption, FPGA, Watermarking
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