International Journal of Engineering and Technology

The traditional system on chip designs employ the shared bus architecture for data transfer in highly integrated Multiprocessor system on chips(MPSoC).Network on chip (NoC)is a new paradigm for on chip communication for Multiprocessor systems on chips(MPSoCs). NoCs replace the traditional shared buses system with routing switches. Heart of the NoC is the router and it consists of an input buffer, arbiter, crossbar and an output port. The NoC router uses a buffer to store the incoming packets. These buffers improve the performance but they consume more power and area. Bufferless deflection routing is the solution for improvement in energy efficiency. In this method deflections of the packets take place to overcome the contention problem. But at high network load, deflection routing degrades the performance because of unnecessary hopping of data packets. The MinBD (minimally buffered deflection) router is a new router design that uses a small buffer for bufferless deflection routing. In this paper the input block of MinBD router is implemented on FPGA which shows that a small buffer will help to reduce the network deflection rate. It also improves the performance and energy efficiency while buffering only deflected data packets.